Nonlinear nonsingular feedback shift registers

ABSTRACT

Four classes of nonlinear nonsingular feedback shift registers (NLFSR) are disclosed. Each NLFSR, assumed to be r stages long, regardless of its class, generates a feedback sequence of length 2r. The sequence is one which cannot be completely deciphered by one not knowing the feedback arrangement, unless at least a very significant portion of the sequence, which is much greater than 2r-1 successive bits is known. Each NLFSR of either class 1 or class 2 has a feedback arrangement which is a function of a primative polynomial of degree r-1. Each register of class 1 includes three nonlinear terms, each one of which is the AND function of a different combination of (r-1) outputs of the first (r-1) stages. Each register of class 2 includes a single nonlinear term which is the AND function of (r-1) outputs of the first (r-1) stages. Each NLFSR in class 3 has a feedback arrangement which is based on a primative polynomial of degree r2 and a unique single nonlinear term, while each NLFSR in class 4 has a feedback arrangement which is based on a primitive polynomial of degree r-3 and three nonlinear terms.

United States Patent [191 Fletcher et a1.

[451 Oct. 7, 1975 invention of Marvin Perlman, Granada Hills, Calif.

22] Filed: Aug. 27, 1974 21 Appl. No.: 501,012

[52] US. Cl 328/37; 307/221 R; 235/92 SH [51] Int. Cl. GllC 19/20; HO3K 23/00 [58] Field of Search 328/37; 235/92 SH; 307/221 R [56] References Cited UNITED STATES PATENTS 3,439,279 4/1969 Guanella 328/37 3,535,642 10/1970 Webb 328/37 3,718,863 2/1973 Fletcher 328/27 3,725,791 4/1973 Moreau et a1. 328/37 3,816,764 6/1974 King 328/37 Primary ExaminerStanley D. Miller, Jr. Attorney, Agent, or FirmMonte F. Mott; Paul F. McCaul; John R. Manning ABSTRACT Four classes of nonlinear nonsingular feedback shift registers (NLFSR) are disclosed. Each NLFSR, assumed to be r stages long, regardless of its class, generates a feedback sequence of length 2. The sequence is one which cannot be completely deciphered by one not knowing the feedback arrangement, unless at least a very significant portion of the sequence, which is much greater than 2r-l successive bits is known. Each NLFSR of either class 1 or class 2 has a feedback arrangement which is a function of a primative polynomial of degree r-l. Each register of class 1 includes three nonlinear terms, each one of which is the AND function of a different combination of (r-l) outputs of the first (r1) stages. Each register of class 2 includes a single nonlinear term which is the AND function of (r-l) outputs of the first (r-l) stages. Each NLFSR in class 3 has a feedback arrangement which is based on a primative polynomial of degree r-2 and a unique single nonlinear term, while each NLFSR in class 4 has a feedback arrangement which is based on a primitive polynomial of degree r-3 and three nonlinear terms.

20 Claims, 15 Drawing Figures US. Patent Oct. 7,1975 Sheet 1 of9 3,911,330

2 i r-l r FEED BACK STAGE FIG. 6b

US. Patent 00. 7,1975 Sheet 5 of9 3,911,330

US. Patent Oct. 7,1975 Sheet 6 of9 3,911,330

I l I I l I 2 3 4 FIGII NONLINEAR NONSINGULAR FEEDBACK SHIFT REGISTERS ORIGIN OF INVENTION 'The invention described herein was made in the performance of work under a NASA contract and is subject to the provisions of Section 305 of the National Aeronautics and Space Act of 1958, Public Law 85-568 (72 Stat. 435; 42 USC 2457).

BACKGROUND OF THE INVENTION l. Field of the Invention The present invention relates to feedback shift registers, and more particularly, to four new classes of nonlinear feedback shift registers, each register or r stages generating a single cycle of 2 states.

2. Description of the Prior Art The construction and use of many types of feedback shift registers (FSRs) are well known. Basically, in a FSR of r-stages, the outputs of various stages are combined in a feedback network to generate a feedback bit which is fed back as the input to the first stage. If the individual outputs of the various stages are modulo-2 summed the FSR is referred to as a linear FSR or LFSR. If the output of the last stage is modulo-2 summed with any switching function of one or more of the outputs of the (r-l stages, such as FSR is often referred to as a nonsingular FSR. Generally, to obtain the longest possible cycle (sequence) with an r-stage FSR the output of the last stage is modulo-2 summed in the feedback stage. Thus, every LFSR is in fact a linear nonsingular FSR.

When the stages whose outputs are modulo-2 summed are selected as a function of the exponents of a primitive polynomial of degree r, two disjoint cycles are generated. One is of length 2'1 and the other is of length 1. Thus, the longest cycle which can be generated with an r-stage LF SR is of length 2 -1. The 2] successive feedback bits represent a 2l PN sequence with noise-like properties. Such sequences have been used for various data transmission applications. It can be shown that even though 2l may be made quite long by choosing a large value of r, if only a small portion of the long sequence, generated by an LFSR is known the entire sequence can be determined therefrom as well as the feedback arrangement employed to generate the sequence. Generally, if 2r1 bits of a sequence of 2l generated with a LFSR, are known the entire sequence can be determined.

OBJECTS AND SUMMARY OF THE INVENTION It is a primary object of the present invention to provide r-stage nonlinear nonsingular feedback shift registers, each of which generates a single cycle of 2 states.

Another object of the present invention is to provide four distinct classes of r-stage nonlinear nonsingular feedback shift registers, each one of which generates a sequence of 2 bits, the sequence being one which cannot be determined unless a very long portion thereof, significantly greater than 2r-1 successive bits, are known.

These and other objects of the present invention are achieved by each nonlinear nonsingular feedback shift register, hereinafter defined as NLFSR, which includes a feedback arrangement based on a primitive polynomial of a degree less than r and at least one nonlinear term which is the AND function of r-l outputs of the first (r-l) stages of the register, one output per stage. All the NLFSRs in accordance with the present invention, are divided into four classes.

Each NLFSR of either class 1 or class 2 has a feedback arrangement which is a function of a primitive polynominal of degree r-l. Each register of class 1 includes three nonlinear terms, each one of which is the AND function of a different combination of (r-l) outputs of the first (r-l stages. Each register of class 2 includes a single nonlinear term which is the AND function of (rl) outputs of the first (r-l) stages.

Each NLFSR in class 3 has a feedback arrangement which is based on a primitive polynomial of degree r-2 and a unique single nonlinear term, whle each NLFSR in class 4 has a feedback arrangement which is based on a primitive polynomial of degree r-3 and three nonlinear terms.

Each of the NLFSRs, regardless of its class, generates a feedback sequence of length 2'. The sequence is one which cannot be completely deciphered by one not knowing the feedback arrangement, unless at least a very significant portion of the sequence, which is much greater than 2rl successive bits, is known.

The novel features of the invention are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in conjunction with the accompanying drawmgs.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a general block diagram of a feedback shift register;

FIG. 2 is a general block diagram of a nonsingular feedback shift register;

FIG. 3 is a general block diagram of a feedback shift register of the present invention;

FIG. 4 is a list of different inputs for a term C included in the feedback arrangement of a 5-stage NLFSR of class l of the present invention;

FIGS. 5a and 5b are diagrams useful in the explaining a prior art type LFSR of 5 stages;

FIGS. 6a and 6b are diagrams useful in explaining how the LFSR shown in FIG. 5a is converted into a class 1 NLFSR in accordance with the present invention;

FIGS. 7 and 8 are diagrams useful in explaining a class 2 NLFSR;

FIGS. 9 and 10 are diagrams useful in explaining a class 3 NLFSR embodiment;

FIGS. 11 and 12 are diagrams useful in explaining a class 4 NLFSR embodiment; and

FIG. 13 is a diagram of one embodiment of a 50-stage NLFSR of class 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before proceeding to explain the present invention, a generalized r-stage binary feedback shift register will first be discussed. An r-stage binary feedback shift register (FSR) in its most general form appears in FIG. 1. The stages are designated 5 -8,. The content of the i" stage S; at clock pulse interval (CPI) k is denoted by a,,. The bit being fed back at CPI k is denoted by a where k f( k1 lt--23 ifilm-+1 ir-r) and f is a switching function of the Boolean variables The content of the 1' stage at CPI k becomes the content of the (i+l stage at CPI k+l. That is,

The initial state of the stage is denoted by a i (i.e., I\=()) where a,, denotes the bit being fed back at CPI k=0.

The state of the FSR at CPI k is an r-tuple of binary digits represented by a,,. a a; ,a Distinct states a, ,a, a, a, and b b,,. where a, b, for at least one value of 1', i=1, 2, rl, r will have distinct successor states if and only if the feedback function is of the following form.

where the symbol denotes the modulo-2 sum, i.e., Exelusive-Or.

The feedback functionf, in (3) is regarded as nonsingular since it is a function of the modulo-2 summation of the output of the last stage S,., i.e., a and F, where F is an arbitrary switching function of the outputs of one or more of the first r-l stages. A feedback shift register (FSR) having a nonsingular feedback function is termed a nonsingular FSR. A generalized embodiment of such a FSR is shown in FIG. 2. If F is a function of only the Exclusive-Or of various outputs of stages S S,. then the FSR is termed a linear FSR, designated LFSR. Every LFSR is by definition nonsingular. If, however, F includes a term which is a nonlinear switching function of several outputs which is in turn modulo- 2 summed with other outputs of stages S S,. then the FSR is termed a nonlinear nonsingular FSR or NLFSR. For example, if F a a, a a, 'a 2, then F is not linear and therefore the FSR is a NLFSR. The present invention is directed to several classes of NLFSRs.

Before proceeding to describe the invention the above used notations will be simplified for the following discussion. The CPI k will be implied when possible follows:

That is, the output of stages S,S,v instead of being denoted as a a. a a, will be denoted as a, a,.. However, the feedback bit 11, will be designated as such in order not to confuse it with the letter *a". In accor dance with the present invention, each stage such as the ith stage, S,- being a binary stage, has an assertion output and a negation output, hereinafter designated a, and 11,-. As is known, the assertion output a; is high or a I when the stage stores a l and is low or a when the stage stores a 0. Similarly, the negation output, a,- is a l (or 0) when a (or 1 is stored in stage S,-.

FIG. 3 is a generalized block diagram of the NLFSR of the present invention shown consisting of r stages and a feedback stage 10 to which all the assertion and negation outputs of all the stages are shown connected for explanatory purposes. In practice, only selected ones of the outputs are used therein. The output a of the feedback stage 10 is fed back to the first stage 8,. As is known, when the register is clocked by a clock (not shown) stage S stores a and each other stage S 8,. stores the binary digit or bit previously stored in its preceding stage. In network 10, one of the outputs of the last stage S is modulo-2 summed with at least one of the outputs of the first (rl) stages and with at least one term which is the AND product of one output of each of the (r-l stages. It is the latter term (or terms) which introduce the nonlinearity in the feedback function and which contribute to the advantages thereof. Basically, the present invention consists of four different classes of NLFSRs. Each NLFSR generally assumed to be of r stages, where r 2 5 is one which generates a single cycle of 2 successive states. The feedback output a is thus a sequence of 2 binary digits or bits. Each of the classes of the NLFSRs of the present invention will now be discussed.

CLASS 1 In this class the feedback signal a is the modulo-2 summation of the assertion outputs of those stages of the register defined by the characteristic polynomial where (1),., (x) represents a primitive polynomial of degree r-l, and 3 additional terms, defined as A, B, C, where The term C is the AND product of all the outputs of all the first (r-l) stages, one output per stage, where at least one of the outputs is an assertion output and at least one is a negation output. For a S-stage register, C can be any of the 14 combinations listed in FIG. 4.

An r-stage register with such a feedback arrangement cycles through all the possible 2* stages regardless of its initial stage. Thus, the register output a is a sequence of 2 bits. This point will be clearly shown hereinafter. Furthermore, the number of possible sequences which can be generated as (2'*2) times the number of primitive polynomials of degree r-l. Thus, a very large number of unique sequences, each 2 long, can be generated. As will become apparent from the foregoingn discussion, the nonlinear terms i.e., A, B and C which are modulo-2- summed in the feedback stage 10 cause the disjoined cycles which the r-stage register would produce if the feedback function were only that defined by the characteristic polynomial to join into a single cycle of 2* states.

This point may best be explained with specific examples. FIG. 5a is a diagram of a 5 stage (r=5) prior art LF SR, whose feedback function is defined by the characteristic polynomial where l+x+x is a primitive polynomial of degree 5l=4. Therefore, a a a a Numerals 21 and 22 designated modulo-2 summers in the feedback stage 10, with the output of summer 22 representing a,,..

When 0,, is fed back to S the S-stage register, which is a LFSR, generatess 4 disjointed cycles. Two are associated with complementary sequences each of length 2' l, i.e., 2 l and 2 are" isolated 1 state cycles, one of all zeros, 00000, and one of all ones, lllll. Such four cycles are shown in FIG. 5b.

In accordance with the present invention, the prior art LFSR is converted into a NLFSR by including in the feedback network three AND gates which generate the terms A, B and C which are modulo-2 summed with a;

+ a a Such an arrangement is shown in FIG. 6a, wherein the three AND gates are designated by numerals 25, 26 and 27. The outputs of gates -27 respectively represent A, B and C. In the particular example, C l n2 3 4- In this embodiment, a cycle of length 2 32 is generated. Assuming an initial state of all zeros, a complete cycle is shown in the left section of FIG. 6b. The 32 bits under the column designated a can be used as the registers output.

It should be pointed out that by merely changing the four intputs to gate 27 a different C term is produced, resulting in a different 32-state cycle. For example, with C a,a a a the 32-state cycle and the 32-bit sequence shown on the right section of FIG. 6b are produced. Indeed using the same arrangement by merely changing the inputs to gate 27, 14 different sequences can be generated. Clearly, 14 different sequences can be generated for each primitive polynomial of degree 5-1fl.

It should be apparent that the invention is not limited to a S-stage register. The number of stages can be any number greater than 4 since for any number of stages of 5 or more there exists primitive polynomials of degree one less than the number of stages. It should further be apparent that the register shown in FIG. 6a is non-singular since the output of the last stage, i.e., a is effectively mod-2 summed with the term F which in the particular example is equal to a a A B C.

There are several significant advantages which result from the present invention. The first advantage is that with each register of Class 1 a sequence of 2 states or bits can be generated. With prior art registers only a sequence of 2* 1 bits is possible. More importantly, however, the 2 sequence generated by the register in accordance with the invention is such that it is practically impossible to reconstruct the entire sequence and, thereby determine the structure of the register, unless the entire sequence length of 2' states is known. Such a property maybe used to great advantage to produce an encoding sequence or key for. enciphering and decipheringdata, represented as a sequence of binary digits or bits. If the enciphered data is communicated, it will be secure from use by unauthorized users as long as the entire sequence or key is not shown. This may be illustrated as follows:

Dataisequence ()1 10101 ll I01 100 Key 111101011001000 Cipher l00llll00l00l00 Cipher IOOIIIIOOIOOIOO Key IIIIOIOIIOOIOOO Datasequence OllOIOllllOllOO Actually, decipherment involves an inverse transformation whereby the key is subtracted bit-by-bit modulo 2 from the cipher, yielding the data sequence. Since 1 I! l modulo 2, bit-by-bit modulo 2 subtraction and addition are equivalent. Thus, T, T,-.

When a key possesses randomness properties and its length exceeds the total length of all the data sequences, decipherment without the key is literally impossible. PN sequences such as those shown above length 15, though finite in length have noiselike properties. Such PN sequences are produced by prior art LFSRs as well as by the NLFSRs of the present invention. Thus, they can be used as the key.

One disadvantage of the type of sequences generated with a prior art LFSR is that due to the linearity, if a small portion of the key or sequence is known, the rest of the sequence can be determined therefrom. For example, assume that the PN sequence is generated by an LFSR of 50 stages, i.e., r=50 and that the sequence length is 2 I. It can be shown that if at least 250 l l 99 successive bits of the sequence are known the rest of the sequence can be determined and therefrom the structure of the register. Thus, keys generated with an LFSR are not sufficiently satisfactory to seucre the data from unauthorized use.

However, the sequence generated with any NLFSR of Class I in accordance with the present invention, due to the nonlinearity the entire sequence cannot be determined from a short portion thereof. The bits of a relatively long portion of the sequence much much longer than Zr-l must be known to determine the register structure. If r is made relatively large, even with a high clocking rate, the sequence can be made so long that its cmoplete generation takes many years, thus, making key breaking practically impossible. For example, with r=50 with the present invention, a sequence of 2 10 can be generated. Assuming a clocking rate of 1 MHz it would take more than 30 years to generate the entire sequence.

These advantages are possessed by sequences which can be generated by any of the registers following within Class 1 or by any register in any of the following classes of NLFSRs in accordance with this invention.

CLASS 2 Consider an r-stage FSR with a feedback function represented by In the above expression f,,(x) designates the assertion outputs of the stages which are to be fed back and modulo-2 summed and the term (1+x) in f (x) indicates that the feedback bit is the complement of the modulo-2 summation of the outputs defined by fi,(x). Such a register is a LFSR which generates two disjointed cycles, one of length 2"2 and the other of length 2. In accordance with the present invention a nonlinear term defined as A is included in the feedback function to convert the register into a NLFSR which generates a single cycle of 2' states. The term A is the AND product of the outputs of the first (r-l) stages, one output per stage, with every other output being the assertion output and every other output is the negation output. Thus, A can be defined as follows:

A, =a a 'a -,a 'a

A a,a a 'a a,,'.

The differences between a conventional LFSR and the NLFSR of the present invention can best be explained in connection with the following examples together with FIGS. 7 and 8. Let r=5 and qS x 1:. Thus,

f,,(x)=(l+x)(l+x+x 1+ x +x -i-x Therefore, the feedback bit (9,. is defined by f,,(x) as a a a a and its complement can be expressed where the term 1 indicates a constant of l which is modulo-2 summed with a a a The same can be accomplished by taking the negation output of one of the three stages S S or S Thus, a can be rewritten In the following example, it is assumed that a a a (1 With such a feedback bit the register is a LFSR and it will produce 2 cycles as shown in the right section of FIG. 8. However, in accordance with the present invention the LFSR is converted into a NLFSR with a feedback bit defined as FIG. 7 shows a register with such a feedback arrangement. AND gate 41 provides the term A which in the particular example A a a a a, and numerals 42-44 designate three modulo-2 summers which modulo-2 sum the four terms (1 A and a which define a The register with such a feedback arrangement is a NLFSR which generates a single cycle of 2 =2 32 states, as shown in the left section of FIG. 8.

It should be apparent that instead of output a a a and a outputs a,', a a and a may be supplied to gate 41. In such a case a different 2 length sequence will be produced. Thus, in this class for each primitive polynomial of degree rl two different sequences may be generated. The total number of sequences for this class is two times the number of primitive polynomials of degree (;I

CLASS 3 An r-stage LFSR associated with the characteristic polynomial f|( 0 r2 I )fn(- where f,,(x) l+x) (x), generates two disjoint cycles. In the above expression, d (x), in f,,(x) represents a primitive polynomial of degree r2. The expressionf,,(x) designates the outputs of the stages which are fed back in f (.r). The term (l-l-x) factor 0ff (x) indicates that the feedback signal is the complement of the mod-2 sum of the assertion outputs of the stages defined by f,,(x). The two disjoint cycles are of lengths 2'-4 and 4.

In accordance with this invention such an LFSR is converted into a NLFSR producing a single cycle of length 2* by the modulo-2 addition of the term defined herein as A where In the above expression for A a a 0z, is any one of four of the following r-l tuples:

OOll ...OOI1

l00l...100l...

l100...llOO...

Oll0...0ll0... where a 0 indicates a negation output and a 1 an assertion output.

Thus, the four possible expressions for A are as fol- This indicates that the assertion outputs of stages 5,, S and S should be fed back and mod-2 summed. To feed back the signal a, in accordance with f (x) the complement of this modulo-2 sum is required. Thus, a,,. can be made equal to Also, the complementing may be achieved by modulo- 2 summing the negation output of one of stages 8,, S and S with the assertion outputs of the other two stages. For example, a a" a a With such a feedback signal two cycles are generated as shown in the right section of FIG. 9. However, if the A is modulo-2 summed with a a a a single cycle of 2 states is produced. Let A a a a a Therefore The length 32 cycle for an all zero initial state is shown in the left section of FIG. 9.

An example of a NLFSR with such a feedback arrangement is shown in FIG. 10 where AND gate 51 generates A The single cycle generated with such a feedback arrangement is shown in the left section of FIG. 9 for an initial state of all zero. Clearly, if A were chosen to be any one of the following 2 r -2 3 4 Three different cycles are generated even though a 61 (1 is not changed. Thus, the number or r-stage NLFSRs included in this class is 4 times the number of primitive polynomials of degree r-2.

CLASS 4 Class 4 is similar to Class 3 except that in the latter the feedback function of an r-stage register is a function of the primitive polynomial of degree r3. Let

In the above expressions q5, (x) indicates a primitive polynomial of degree r3, and the expression 1+x) in f (x) indicates that f1(X) is associated with a is the complement of a,,l associated with fl,(x). Such a feedback function when associated with an r-stage LFSR generates two pairs of complementary cycles. One pair is of length 2 4 and the other pair has a length 4. For example, for r=5 and d (x) H- x x By taking the negation output of any of the three stages, S S or 8,, the constant term 1 can be deleted. Thus, a can be rewritten as It can be easily shown that with such a feedback arrangement four disjointed cycles are generated as shown in the right section of FIG. 11. In accordance 20 with the present invention, the four cycles can be joined into a single cycle of 2 states by modulo-2 adding to the linear feedback function the following three terms.

where the r-l tuples [3 8 ,8 B 0 0 0- and 8 8 8;, 6 are independently selected from the states.

0 l 0 l 0 0 u u l 0 1 1 l o l 0 I 0 l l 0 u 0 l 0 i l l l 0 0 0 l 0 l l 0 o l 0 0 l l 0 1 From the possible combinations of B ,8 etc., up to ,8 it is seen that A is the AND function in which every other input is an assertion output of a stage of the r1 stage and every other input is a negation output. If the negation output of S1 is chosen, i.e., a then the assertion output a of S2 is chosen. On the other hand, if a, is chosen, as one of the inputs, then a "is chosen as one of the other inputs.

As to the possible combinations of 0,, 0' through (nthey can be thought of as groups of three negation outputs followed by an assertion output, where the output of S1 can be any one of the four in the group. As shown above in order, the output of S1 can be the negation output followed by the negation outputs of S2 and S3 and assertion output of S4, etc., or it can be the assertion output followed by three negation outputs of S2, S3, S4. Likewise, the output of S1 can be the last negation output in the group of four followed by the assertion output of S2 the negation outputs of S3, S4, S5, etc. The output of S1 can also be the middle negation output of the group followed by the negation, assertion and three negation outputs of S2, S3, and S4-S5, etc., (assuming that r is not less than 6).

As to 6 6 8 they indicate successive groups up to r-l each group of three successive assertion outputs followed by a negation output. Again, the output of S1 can be chosen to represent any one of the four positions in the group. That is, the output of S] can be the assertion output followed by two assertion outputs in which case it is the first assertion of the three; by one assertion output in which case it is the middle assertion output of the three or by a negation output in which case it is the third assertion output of the three. The

output of S1 can also be the negation output in the group followed by three assertion outputs,

Assuming a -stage register and assuming that the first r-l types chosen for each of ,8 8 are and further assuming the previous linear feedback function when the two sets of terms are modulo-2 a NLFSR is produced which generates a single unique 2=2"-32 state cycles, as represented in the left hand section.

FIG. 12 is a diagram of a 5-stage register with such a feedback arrangement. AND gates 61-63 produce A;,A respectively and modulo-2 address 65-69 perform the modulo-2 addition of the 6 terms needed to produce a It should be apparent that there are 32 different combinations of outputs of the stages to generate A,,A Thus, for each primitive polynomial of degree r3, up

to 32 different 2 cycles can be generated.

SUMMARY In accordance with the present invention four classes of NLFSRs are provided. Each register assumed to be r-stages long where r z 5 produces a sequence of 2 states. The feedback function of each register includes l o 1 l at least one nonlinear term. In each register of Class 1 the feedback bit is a function of the assertion outputs of stages defined by the exponents of the terms of the characteristics polynomial f (x) 1+x) ,(.r) which are modulo-2 summed together with three nonlinear terms defined as A, B, and C. The term (x) represents a primitive polynomial of degree r-l and the term A is the AND function of the assertion outputs of all the first (r1) stages. The term B is the AND function of the negation outputs of all the first (r-l stages and the term C is the AND function of the outputs of all the (rl) stages with at least one output being an assertion output and one output being a negation output.

In each register of Class 2 the feedback function is the complement of the modulo-2 sum of the assertion outputs of stages defined by the exponents of the terms of the characteristic polynomial f,,(x) l+x) ,(x), modulo-2 summed with a nonlinear term A The term A is the AND function of the outputs of the first r-l stages, where every other output is an assertion output the terms of a characteristic polynomial f (x) 1+x) (x), modulo-2 summed with a nonlinear term defined as A The term (x) designates a primitive polynomial of degree r2. The term A is the AND function of the r-l outputs of the first rl stages, one

output per stage. Regarding the first r1 stages as arranged in a sequence from 1 to r-l, A may be the AND function of opposite outputs of successive pairs of stages.

For example, A may be the AND function of the assertion (or negation) outputs of the first two stages followed by the negation (or assertion) outputs of the next two stages, followed by the assertion (or negation) outputs of the next pair of stages, etc. Also, A may be the AND function of the assertion (or negation) output of the first stage S followed by opposite outputs of each pair of successive stages.

In each register of Class 4 the feedback bit is a function of the complement of the modulo-2 summation of the assertion outputs of stages defined by the exponents of the terms in the characteristic polynomial modulo-2 summed with three nonlinear terms defined as A A and A A is the AND function of the outputs of the first r-l stages where every other output is a negation output and every other output is an assertion output. A is the AND function of the outputs of all the first r-l stages in which the output of the first stage may be the negation output followed by an assertion output and, thereafter, repeatedly followed by three negation and one assertion output up to (rl outputs. A may also be the AND function of the negation output of the first stage followed by the assertion output of the second stage and thereafter repeatedly followed by three negation outputs and one assertion output. A, may also be the AND function of the assertion output of the first stage followed repeatedly by three negation outputs and one assertion output. A, may also be the AND function of the negation outputs of the first two stages followed repeatedly by an assertion output and three successive negation outputs. Generally, A is the AND function of successive groups of outputs each group of three negation outputs and one assertion output, and the output of S1 may be any one of the four in the basic group.

A like A;, and A is the AND function of (r-l) outputs of the first (rl stages, one output per stage. Basically, these outputs are a repeating succession of three assertion outputs followed by a negation output. The output of the first stage may be the first assertion output of the first group of three assertion outputs, or the negation output preceding the first group of three successive assertion outputs. The outputs of the first two stages may be the assertion and negation outputs preceding the first group of three successive assertion outputs or the outputs of the first three stages may be the assertion, assertion and negation outputs followed by the first group of three successive assertion outputs. Generally, A is the AND function of successive groups of outputs, each group being of three assertion outputs and one negation output, and the output of the first stage S1 may be any one of the four in the basic group.

Each of the NLFSRs in accordance with the present invention generates a single cycle of 2* states. Thus, its output is a sequence of 2 bits. Due to the fact that such a sequence is generated with at least one nonlinear term it practically is impossible to determine the feedback arrangement generating the sequence unless at least a very long portion of the sequence is known.

Although hereinbefore the various classes of NLFSRs have been described in connection with 5- stage NLFSRs the invention is not limited to r=5. The number of stages r may be any integer greater than 4. As is appreciated, the number of primitive polynomials grows as r grows. For example, assuming a register of r=24, there are 356,960 primitive polynomials for degree rl=23.

For example, 1 +x +x +x" x is a primitive polynomial of degree 8. Thus, it can be used to form a 9- stage NLFSR in either Class 1 or 2, a lO-stage NLFSR of Class 3 or a 1 l-stage NLFSR of Class 4. Similarly, l+x +x is a primitive polynomial of degree 49. Thus, it can be used to form NLFSRs or 50, 51 and 52 stages.

The following is an example of deriving a 50-stage NLFSR of Class 2. Let,

where (1+x) indicates that f,(x) is the complement of f,,(x). Therefore, for a LFSR However, for a NLFSR in accordance with the present invention where A may be expressed as I I I I I 7 l l 2 s a s s 7 s 9 10 4s 49 I I I s s io u 4s 49 One embodiment of such a SO-stage NLF SR is shown in FIG. 13. Therein, and gate with 49 inputs generates A Fed to gate 49 are the assertion outputs of all the oddnumbered stages of the first 49 stages and the negation outputs of the even-numbered stages except the last. A different 2 state sequence can be generated by supplying to gate 75 the negation outputs of the oddnumbered stages and the assertion outputs of all the even-numbered stages, except the last stage S Hereinbefore, only exclusive-OR gates were shown in each feedback stage or network to generate the feedback bit a which is the exclusive-OR function of varous outputs of the register stages and at least one AND gate. It should be appreciated that the time required to generate the feedback bit may be optimized by arranging the gates in different operational levels. Also, the feedback bit a may be generated by logic elements other than exclusive-OR gates. For example, in the embodiment shown in FIG. 7,

where A a,a a a It can be shown that where v denotes a logical OR, and where A, is the complement of A,. Thus, the feedback bit a, can be 13 generated with eight 4-input AND gates and one 8- input OR gate in addition to gate 41 and an additional inverter to provide A Therefore, the term modulo-2 summing means as used herein, is intended to include any logic means not limited to exclusive-OR gates capable of providingan output such as the feedback bit a,,. which is the modulo-2 sum of certain outputs of register stages or AND gates. Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art and consequently, it is intended that the claims be interpreted to cover such moficiations and equivalents.

What is claimed ,is:

l. An r-stage nonlinear nonsingular feedback shift register comprising: I

a binary shift register of r stages, arranged in a sequence from 1 to r where r 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level definable as a l, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a feedback means including a first AND gate for providing an output which is the AND function of the assertion outputs of all the first (r'-l stages, a second AND gate for providing an output which is the AND function of the negation outputs of all the first (rl) stages, a third AND gate for providing an output which is the AND function of the outputs of the first (rl stages, one output per stage, where at least one output is an assertion output and at least one output is a negation output, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the outputs of said first through third AND gates and the assertion outputs of stages defined by the exponents of terms in a characteristic polynomial f,,(x) I ,(x), where d (x) represents a primitive polynomial of degree r-l; and

means for feedingback said feedback output to said first stage.

2. An r-stage nonlinear nonsingular feedback shift register comprising:

a binary shift register of r stages, arranged in a sequence from 1 to r, where r 2 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a l, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0;

feedback means including a single AND gate for providing an output which is the AND function of the outputs of said (rl stages, one output from each stage, where the type of output of each stage following the first stage is opposite the type of output of the preceding stage, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the oeutput of said AND gate and the complement of the modulo-2 sum of the assertion outputs of stages defined by the exponents of a characteristic polynomial f,,(x) (1+x) q5 (x), where 75, (x) is a primitive polynomial of degree r-l; and

means for feeding back said feedback output to said first stage.

3. The shift register as described in Claim 2 wherein the output of the AND gate is a function of the assertion outputs of all the odd-numbered stages of said (r 1) stages and the negation outputs of all the even-numbered stages of said (r 1) stages.

4. The shift register as described in claim 2 wherein the output of the AND gate is a function of the negation outputs of all the odd-numered stages of said (rl stages and the assertion outputs of all the evennumbeered stages of said (rl) stages.

5. An r-stage nonlinear nonsingular feedback shift register comprising:

a binary shift register of r stages, arranged in a sequence from 1 to r, where r z 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a l, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0;

feedback means including an AND gate for providing an output which is the AND function of outputs of the first (rl stages, one output per stage, the outputs being alternating pairs of assertion and negation outputs, with the output of the first stage being a negation output followed by the negation output of the second stage and thereafter by alternating pairs of assertion and negation outputs up to (r-l outputs, or the output of the first stage being an assertion output followed by alternating pairs of negation and assertion outputs up to (r-l) outputs, or the outputs of the first two stages being the assertion outputs followed by alternating pairs of negation and assertion outputs up to (rl) outputs, or the first stage output is the negation output followed by alternating pairs of assertion and negation outputs up to (rl) outputs, and modulo-2 summing means for modulo-2 summing the AND gate output and selected outputs of said states to provide a feedback output which is the complement of the modulo-2 sum of said AND gate output and assertion outputs of stages defined by the exponents of terms of a characteristic polynomial, definablle asf,,(x)=(1+x) b, (x), where (x) is a primitive polynomial of degree r2.

6. The shift register as described in claim 5 wherein the AND gate output is a function of the negation output of said first stage.

7. The shift register as described in claim 6 wherein the AND gate output is a function of the negation outputs of said first and second stages followed by alternating pairs of assertion and negation outputs up to (rl outputs.

8. The shift register as described in claim 6 wherein the AND gate output is a function of the negation output of the first stage followed by alternating pairs of assertion and negation outputs up to (rl) outputs.

9. The shift register as described in claim 5 wherein the AND gate output is a function of the assertion output of said first stage.

10. The shift register as described in claim 9 wherein the AND gate output is a function of the assertion output of said first stage followed by alternating pairs of negation and assertion outputs up to (r-l) outputs.

11. The shift register as described in claim 9 wherein the AND gate output is a function of the assertion outputs of the first two stages, followed by alternating pairs of negation and assertion Outputs up to (rl) outputs. defines a primitive polynomial of degree 12. An r-stage nonlinear nonsingular feedback shift I 3; and register comprising: means for feeding back said feedback output to the a binary shift register of r stages, arranged in a sefirst Stage f aid register.

q n from 1 t h r r h t g h ving 5 13. The shift register as described in claim 12 an assertion output which is at an enabling level wherein said modulo-2 summing means are responsive when the state is at a first binary level, definable as t one Output f h f h Stages d fi d b h expoand negation Output Which is at an enabling nents of the terms of said characteristic polynomial, all

level when the stage is at a second binary level, deof the outputs of the defined stages being assertion outfinable as a 0; l puts except one which is the negation output. feedback means including first, second and third The Shift register as described in claim 13 AND gates each respohswe to a dlfferem combma' wherein each of said first, second and third gates is retion of (r-l) outputs, one from each of the first (r-l stages, for providing an output which the AND function of the output supplied thereto, said 15 first AND gate being responsive to a succession of (r-l outputs in which every other output is an assertion output and every other output is a negation output, with the output of the first stage being either an assertion output or a negation output, said second AND gate being responsive to a succession of (r] outputs in which groups of three negation Stageoutputs followed by a single assertion output are 17. The shift register as described in claim 16 repeated successively, with the output of the first wherein said second AND gate is responsive to the nestage being any of the three negation outputs or the gation output of said first stage.

assertion output, said third AND gate being re 18. The shift register as described in claim 16 sponsh'e to a succession of Outputs in which wherein said third AND gate is responsive to the negagroups of three assertion outputs followed by a sinti output f id fi Stage gle negation output are repeated successively, with The hift register as described in claim 12 the Output of the first Stage being any one of the wherein said first AND gate is responsive to the negathl'ee 1155mm"! outputs of hegaho" Output and tion output of said first stge and at least said second or moduk 2 summing means for Providing a feed said third gate is responsive to the assertion output of back output which is the complement of the modui fi t Stagg Sum of the Outputs of said first, second and 20. The shift register as described in claim 19 third gates and the assertion omputs of Stages wherein each of said second and third AND gates is refined by the exponents of the terms of a Character sponsive to the assertion output of said first stage. istic polynomial fi,(x) l+x) (.r) where l sponsive to the negation output of said first stage.

15. The shift register as described in claim 13 wherein each of said first, second and third AND gates is responsive to the assertion output of said first stage.

16. The shift register as described in claim 12 wherein said first AND gate is responsive to the assertion output and at least said second or said third AND gate is responsive to a negation output of said first 

1. An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r where r > OR = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including a first AND gate for providing an output which is the AND function of the assertion outputs of all the first (r-1) stages, a second AND gate for providing an output which is the AND function of the negation outputs of all the first (r-1) stages, a third AND gate for providing an output which is the AND function of the outputs of the first (r-1) stages, one output per stage, where at least one output is an assertion output and at least one output is a negation output, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the outputs of said first through third AND gates and the assertion outputs of stages defined by the exponents of terms in a characteristic polynomial fo(x) phi r 1(x), where phi r 1(x) represents a primitive polynomial of degree r-1; and means for feeding back said feedback output to said first stage.
 2. An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r, where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including a single AND gate for providing an output which is the AND function of the outputs of said (r-1) stages, one output from each stage, where the type of output of each stage following the first stage is opposite the type of output of the preceding stage, and modulo-2 summing means for providing a feedback output which is the modulo-2 sum of the oeutput of said AND gate and the complement of the modulo-2 sum of the assertion outputs of stages defined by the exponents of a characteristic polynomial fo(x) (1+x) phi r 1(x), where phi r 1(x) is a primitive polynomial of degree r-1; and means for feeding back said feedback output to said first stage.
 3. The shift register as described in Claim 2 wherein the output of the AND gate is a function of the assertion outputs of all the odd-numered stages of said (r-1) stages and the negation outputs of all the even-numbered stages of said (r-1) stages.
 4. The shift register as described in claim 2 wherein the outPut of the AND gate is a function of the negation outputs of all the odd-numered stages of said (r-1) stages and the assertion outputs of all the even-numbeered stages of said (r-1) stages.
 5. An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r, where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including an AND gate for providing an output which is the AND function of outputs of the first (r-1) stages, one output per stage, the outputs being alternating pairs of assertion and negation outputs, with the output of the first stage being a negation output followed by the negation output of the second stage and thereafter by alternating pairs of assertion and negation outputs up to (r-1) outputs, or the output of the first stage being an assertion output followed by alternating pairs of negation and assertion outputs up to (r-1) outputs, or the outputs of the first two stages being the assertion outputs followed by alternating pairs of negation and assertion outputs up to (r-1) outputs, or the first stage output is the negation output followed by alternating pairs of assertion and negation outputs up to (r-1) outputs, and modulo-2 summing means for modulo-2 summing the AND gate output and selected outputs of said states to provide a feedback output which is the complement of the modulo-2 sum of said AND gate output and assertion outputs of stages defined by the exponents of terms of a characteristic polynomial, definablle as fo(x) (1+x)2 phi r 2(x), where phi r 2(x) is a primitive polynomial of degree r-2.
 6. The shift register as described in claim 5 wherein the AND gate output is a function of the negation output of said first stage.
 7. The shift register as described in claim 6 wherein the AND gate output is a function of the negation outputs of said first and second stages followed by alternating pairs of assertion and negation outputs up to (r-1) outputs.
 8. The shift register as described in claim 6 wherein the AND gate output is a function of the negation output of the first stage followed by alternating pairs of assertion and negation outputs up to (r-1) outputs.
 9. The shift register as described in claim 5 wherein the AND gate output is a function of the assertion output of said first stage.
 10. The shift register as described in claim 9 wherein the AND gate output is a function of the assertion output of said first stage followed by alternating pairs of negation and assertion outputs up to (r-1) outputs.
 11. The shift register as described in claim 9 wherein the AND gate output is a function of the assertion outputs of the first two stages, followed by alternating pairs of negation and assertion outputs up to (r-1) outputs.
 12. An r-stage nonlinear nonsingular feedback shift register comprising: a binary shift register of r stages, arranged in a sequence from 1 to r where r > or = 5, each stage having an assertion output which is at an enabling level when the state is at a first binary level, definable as a 1, and a negation output which is at an enabling level when the stage is at a second binary level, definable as a 0; feedback means including first, second and third AND gates each responsive to a different combination of (r-1) outputs, one from each of the first (r-1) stages, for providing an output which the AND function of the output supplied thereto, said fiRst AND gate being responsive to a succession of (r-1) outputs in which every other output is an assertion output and every other output is a negation output, with the output of the first stage being either an assertion output or a negation output, said second AND gate being responsive to a succession of (r-1) outputs in which groups of three negation outputs followed by a single assertion output are repeated successively, with the output of the first stage being any of the three negation outputs or the assertion output, said third AND gate being responsive to a succession of (r-1) outputs in which groups of three assertion outputs followed by a single negation output are repeated successively, with the output of the first stage being any one of the three assertion outputs or the negation output, and modulo-2 summing means for providing a feedback output which is the complement of the modulo-2 sum of the outputs of said first, second and third gates and the assertion outputs of stages defined by the exponents of the terms of a characteristic polynomial fo(x) (1+x)3 phi r 3(x) where phi r 3(x) defines a primitive polynomial of degree r-3; and means for feeding back said feedback output to the first stage of said register.
 13. The shift register as described in claim 12 wherein said modulo-2 summing means are responsive to one output of each of the stages defined by the exponents of the terms of said characteristic polynomial, all of the outputs of the defined stages being assertion outputs except one which is the negation output.
 14. The shift register as described in claim 13 wherein each of said first, second and third gates is responsive to the negation output of said first stage.
 15. The shift register as described in claim 13 wherein each of said first, second and third AND gates is responsive to the assertion output of said first stage.
 16. The shift register as described in claim 12 wherein said first AND gate is responsive to the assertion output and at least said second or said third AND gate is responsive to a negation output of said first stage.
 17. The shift register as described in claim 16 wherein said second AND gate is responsive to the negation output of said first stage.
 18. The shift register as described in claim 16 wherein said third AND gate is responsive to the negation output of said first stage.
 19. The shift register as described in claim 12 wherein said first AND gate is responsive to the negation output of said first stge and at least said second or said third gate is responsive to the assertion output of said first stage.
 20. The shift register as described in claim 19 wherein each of said second and third AND gates is responsive to the assertion output of said first stage. 